Photonic Quantum Computing
Thin-Film Lithium Niobate Optical Switch Insertion Loss Drops to 7 mdB
Xanadu and HyperLight have leveraged thin-film lithium niobate (TFLN) fabrication to reduce the insertion loss of integrated optical switches to 7 millidecibels (mdB)[28]. This figure cuts nearly two-thirds off the previous public record (down from approximately 20 mdB to 7 mdB), advancing into the fault-tolerance threshold range for integrated photonic devices. Benchmarked against the current photonic SOTA, while single-switch loss sets a new public record, photonic systems still cannot qualify full-system capabilities based on an isolated component without the backing of a comprehensive end-to-end loss budget (incorporating detection efficiency and photon indistinguishability); practical fault tolerance still lacks high-yield inter-chip optical interconnects and integrated superconducting nanowire single-photon detectors exceeding 95% overall efficiency[28]. This progress directly benefits silicon photonics and lithium niobate photonic quantum roadmaps, potentially scaling single-stage switch network sizes of measurement-based fault-tolerant photonic quantum processors by an order of magnitude within 2 to 3 years and technically replacing traditional thermo-optic microring switch approaches.
Coherent Optical Fiber Connects Two Independent Dilution Refrigerators Across 10 Kilometers
A research team has successfully linked two dilution refrigerators operating in the millikelvin regime using a 10-kilometer coherent optical fiber link, demonstrating universal two-qubit logic gates with controlled fidelity across this long-distance connection[42]. The experiment expands the physical distance of coherent interconnects between cryogenic systems from benchtop scale (several meters) to 10 kilometers—an increase of more than 230-fold. Compared with the current photonic chip-to-chip interconnect SOTA (PsiQuantum’s 99.72% fidelity over 42 meters of fiber), this milestone demonstrates for the first time the feasibility of coherent quantum state transfer between kilometer-scale cryostats; however, microwave-to-optical quantum frequency conversion efficiency and signal-to-noise ratios still lag significantly behind local gate fidelities on superconducting chips (such as IBM Heron's 99.5% to 99.9%), leaving coherent transmission loss as the core bottleneck constraining fault-tolerant interconnects[42]. This advance clears physical topology hurdles for building modular quantum supercomputing centers, driving national quantum network investment cycles to leapfrog from intra-datacenter rack-to-rack interconnects toward inter-campus backbone networks ahead of schedule.
Netherlands Forms National Consortium to Target 100-Qubit Photonic Quantum Computer
Dutch photonic quantum company QuiX Quantum is spearheading a national consortium of eight industrial, academic, and research institutions, officially launching a three-year sprint to deliver a universal photonic quantum processor with over 100 physical qubits by December 2028[29]. The project focuses on tackling three core engineering bottlenecks: photon loss, high-sensitivity detection, and on-chip nanosecond-scale high-speed control[29]. Europe’s photonic quantum ecosystem is leveraging national missions to unite foundries and system integrators, accelerating ecosystem parity with North American photonic quantum startups.
Superconducting and Flux Quantum Computing
IBM Opens Pulse-Level Control on Nighthawk r2 Processor
At the 2026 Quantum Developer Conference, IBM showcased the Nighthawk r2 processor, which integrates 120 programmable qubits, supports sample rates of up to 100,000 per second, and opens pulse-level control interfaces for the first time, enabling developers to execute 64-qubit full-circuit validation experiments[52]. While this extends pulse-level control degrees of freedom to a 64-qubit scale, under current SOTA benchmarks, the processor's full-chip median two-qubit gate fidelity has not been publicly confirmed to surpass Heron r2’s 99.5%, and given fluctuations from two-level system (TLS) defects inherent to superconducting hardware, coherence maintenance in deep 64-qubit circuits still faces high-frequency dynamic calibration challenges[52]. Granting access to pulse-level interfaces allows third-party software and algorithm developers to bypass conventional logic gates and compile noise-resilient protocols directly at the underlying waveform level, shortening validation cycles for fault-tolerant circuits.
IBM Discloses Nighthawk r3 1,000-Qubit Multi-Chip Stitching Roadmap
IBM has unveiled a new hardware roadmap milestone: the next-generation Nighthawk r3 processor will scale single-chip capacity to 520 physical qubits supporting 10,000 quantum operations, with plans to stitch two chips together via chip-to-chip interconnect technology in 2027 to achieve a system running over 1,000 qubits[53]. This signals that the superconducting hardware mainstream has officially pivoted from simple single-chip stacking toward high-fidelity multi-chip modular integration; in contrast to the lower fidelity metrics of the earlier 1,000-qubit Condor chip, this architecture emphasizes executable circuit depth at high gate fidelities[53]. This applies direct competitive pressure on Google Willow and neutral-atom large-array roadmaps, establishing 2027 as the decisive year for proving the practical utility of modular 1,000-qubit superconducting systems.
On-Chip Engineered Dissipation Achieves Ultra-Fast 48-Nanosecond Reset
Researchers have implemented an on-chip engineered dissipation mechanism on a superconducting quantum chip to realize ultra-fast qubit reset in just 48 nanoseconds[50]. Compared to the hundreds-of-microseconds coherence times in superconducting SOTA benchmarks, a 48-nanosecond reset substantially slashes the idle latency per error-correction syndrome extraction cycle; however, whether the additional on-chip dissipation structure induces parasitic Purcell decay during standard gate operations warrants rigorous subsequent evaluation[50]. If standardized for fabrication lines, this reset scheme could boost surface code (the mainstream topological quantum error correction code) cycle clock frequencies by several fold, providing immediate technical support for chipmakers designing low-latency error-corrected processors.
Picosecond Pulse-Driven Flux Qubit Fidelity Exceeds 99.99%
A research team utilized picosecond single-flux-quantum (SFQ, high-speed superconducting pulse) pulses generated by Josephson digital circuits to drive fluxonium qubits (highly anharmonic superconducting qubits), achieving a single-qubit gate fidelity exceeding 99.99% in a low-frequency operating regime[54]. This single-qubit gate benchmark matches the SOTA limits of trapped-ion and silicon donor systems (single-qubit gate fidelity ≥ 99.95%); nevertheless, fault-tolerant computing still lacks experimental validation of high-fidelity two-qubit gates driven by SFQ pulses, and stimulated leakage suppression in low-frequency fluxonium remains unresolved[54]. This validates the feasibility of co-integrating cryogenic digital control logic with quantum chips on a single die, providing a hardware prototype to eliminate bulky room-temperature RF cabling constraints.
63 Superconducting Qubits Successfully Simulate Electric Flux String Dynamics
Physicists have successfully simulated the dynamic evolution and confinement dynamics of electric flux strings in gauge theories on a 63-superconducting-qubit processor[51]. Utilizing a programmable 63-qubit superconducting array to observe non-equilibrium high-energy physics dynamics overcomes the computational truncation bottlenecks of classical numerical simulations in strongly entangled many-body systems[51].
Neutral Atoms and Solid-State Spins
Dual-Species Neutral Atom Crosstalk Error Suppressed Below 10⁻⁴
Researchers have proposed a universal fault-tolerant architecture based on globally driven dual-species neutral atom (laser-trapped atomic system) arrays. Numerical simulations show that inter-atomic crosstalk (unintended adjacent qubit interference) is suppressed below 10⁻⁴ (one in ten thousand), deriving an error correction threshold of 1.43% for quantum memory and a magic state (critical pure state for fault-tolerant computation) logical error rate below 10⁻⁹ (one in a billion) under experimentally accessible Rydberg transition strengths[43]. With crosstalk error falling below the 10⁻⁴ threshold for the first time, the 1.43% error correction threshold surpasses the theoretical ~1% fault-tolerance threshold of standard 2D surface codes. Benchmarked against neutral-atom SOTA (Harvard’s 99.5% physical two-qubit gate fidelity and QuEra’s 96 logical qubits), this architecture theoretically eliminates physical-layer error correction barriers; however, physical hardware realization remains constrained by the platform's low 1–10 Hz cycle repetition rate and the engineering maturation of high-fidelity non-destructive mid-circuit measurements[43]. This enhances the competitiveness of neutral atoms in realizing ultra-low physical-to-logical qubit overheads, putting architectural diversification pressure on superconducting roadmaps pursuing massive physical qubit counts.
Non-Destructive 3D Characterization Breakthrough in 2D Dopant Layers
In a paper published in npj Quantum Information, researchers demonstrated element-specific, non-destructive 3D profiling of 2D dopant layers in silicon semiconductors[7]. This establishes a non-destructive metrology tool for atomically precise silicon spin qubit chips. Compared with Silicon Quantum Computing's (SQC) SOTA benchmark of 99.99% two-qubit gate fidelity achieved in late 2025, this measurement technique resolves yield blind spots caused by the spatial stochasticity of atomic-scale dopants[7]. It accelerates the transition of silicon quantum computing from laboratory lattice samples to commercial semiconductor foundry processes, erecting metrological moats for Australia's SQC and European silicon quantum programs.
Silicon Quantum Computing Appoints Semiconductor Volume-Production Expert to Drive Chip Manufacturing
Australia's Silicon Quantum Computing (SQC) has appointed W.H. Teh as Chief Manufacturing Officer to oversee the scaled volume manufacturing of atomically precise semiconductor quantum chips[74]. This indicates that leading players in the silicon spin arena are pivoting decisively from academic validation to wafer-scale fabrication engineering, shifting organizational talent from theoretical physicists toward commercial semiconductor manufacturing experts.